Course ID: | CSEE 2220E. 3 hours. |
Course Title: | Fundamentals of Logic Design |
Course Description: | Techniques to design digital logic circuits. Topics covered are Boolean algebra, logic of propositions, minterm and maxterm expansions, Karnaugh maps, Quine McCluskey methods, general combinational circuit design, multiplexers, and decoders. The syllabus includes simulation, realization through standard logic families, and realization through programmable logic devices. |
Oasis Title: | Fundamentals of Logic Design |
Duplicate Credit: | Not open to students with credit in CSEE 2220 |
Nontraditional Format: | This course will be taught 95% or more online. |
Prerequisite: | CSEE 2210 or ECSE 1100 or ECSE 1100E or ESCE 1100H or ELEE 1030 |
Semester Course Offered: | Offered every year. |
Grading System: | A-F (Traditional) |
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Course Objectives: | By the end of this course, students should have
– obtained knowledge on logic functions and Boolean algebra
– learned how to apply formal design methods (minimization methods), the Karnaugh Table and the Quine-McCluskey method
– gained the ability to formalize a problem and convert it into a logic expression and then into a circuit on the gate level
– obtained an overview how a gate-level circuit can be realized using integrated circuits and programmable logic |
Topical Outline: | 1. Introduction: Digital systems and binary numbers.
2. Components of digital systems. Basic logic functions.
3. Boolean algebra. Algebraic terms, fundamental theorems. Principle of duality. DeMorgan’s theorems.
4. Boolean functions. Truth tables, disjunctive and conjunctive normal from, complements, lexicographic order.
5. Minterms and maxterms. Canonical representations of Boolean functions. Standard forms.
6. Simplification of Boolean expressions. The Karnaugh map method. 2-level simplification.
7. Simplification (2): Quine-McCluskey method. Petrick’s method.
8. Realization using gates. NAND/NOR networks, NAND/NAND networks, NOR/NOR networks, interconversion between, and benefits of, networks. General combinatorial logic.
9. Number systems (binary, decimal, hexadecimal). Addition. Unsigned and signed numbers. 1's complement and 2's complement. Subtraction. Addition and subtraction circuits at the gate level.
10. Multiplexers and decoders.
11. Gate delays. Simple timing model. Simulation of combinatorial circuits. Propagation delay. Static and dynamic hazards. Elimination of timing hazards.
12. Memory elements.
13. Sequential logic. State diagrams. Formal design of sequential circuits.
14. ROM and RAM as logic tables in combinatorial and sequential circuits.
15. Programmable logic: Gate arrays, PAL/GAL, FPLA. Logic design and programming tools. |
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academic dishonesty of others." All academic work must meet the standards contained in this Code and in A Culture of
Honesty. Students are responsible for informing themselves of those standards before performing any academic work. |